% representing logic circuits using one- and two-input gates
%    and, or, nand, nor, xor, xnor,
% but using inv for negation

% define the behaviour of the individual gates,
% (the last value is the gate output, the first value(s) are the inputs)

inv(false, true).
inv(true, false).

and(true, true, true).
and(false, false, false).
and(false, true, false).
and(true, false, false).

or(true, true, true).
or(false, true, true).
or(true, false, true).
or(false, false, false).

nand(false, false, true).
nand(false, true, true).
nand(true, false, true).
nand(true, true, false).

nor(true, false, false).
nor(false, true, false).
nor(true, true, false).
nor(false, false, true).

xor(true, false, true).
xor(false, true, true).
xor(true, true, false).
xor(false, false, true).

xnor(true, false, false).
xnor(true, true, true).
xnor(false, false, true).
xnor(false, true, false).

% --- define a test circuit ---

% circuit 1: a simple sum-of-products circuit where F is xz' + x'y
%    (uses locals L1, L2, L3, L4 to represent the lines between gates)
circuit1(X,Y,Z,F) :- inv(X, L1), inv(Z,L2),
                     and(X,L2,L3), and(Y,L1,L4),
                     or(L3,L4,F).

% use findall to group all combinations of X,Y,Z that make F true for circuit 1
test1:- format("Detecting circuit 1 minterms [X,Y,Z]:~n   "),
        findall([X,Y,Z], circuit1(X,Y,Z,true), Results), write_ln(Results).